1. Technical Field
The present invention relates generally to digital processing circuits, and more particularly, to a digital circuit having selectable processing stages for controlling operating power levels.
2. Description of the Related Art
Portable devices employ a high degree of energy management in present designs and battery life is a critical performance factors in portable devices and systems. Often, resources are not being used to their full capability and during intervals at which resource demand is low, performance can be traded off for power savings without compromising computing or other results.
Control of energy usage via power/performance tradeoffs is well known in digital processing circuits. Typically, the operating voltage level of complementary metal oxide semiconductor (CMOS) circuits and other similar technologies is varied to control the power consumption of a digital circuit. Reduction of the power supply voltage reduces power consumption with a consequent reduction in performance-controlling factors such as maximum frequency of operation and noise margin.
In processing systems, the above technique is employed in dynamic voltage scaling (DVS) power management. Such systems require a complex voltage regulator to ensure that good power supply integrity is provided over the operating supply voltage range and under the dynamic control conditions. The digital circuits themselves also must be designed to operate over the dynamically controlled power supply voltage range, which introduces compromises that produce less-than-ideal operation at any given voltage level and limits the types of technologies that can be used.
Further, DVS has a high level of transition latency and transition energy that limits the rate at which the power supply voltage can be changed for efficient operation. Transition energy is the energy wasted in changing to a new operating voltage and transition latency is the processing delay incurred while the transition is made. Finally, DVS is a system level approach that is applied across an entire processor or other large-scale logic circuit. Higher energy savings can be provided by more fine-grained control that can take into account which units within a system have high processing resource demand and which units have low processing resource demand.
Another existing power management approach is clustered voltage scaling (CVS). However, CVS is not a dynamic technique that can adapt power consumption to resource demand, but rather assigns different voltages at design time, placing higher supply voltages on circuits requiring higher performance and lower supply voltages on circuits that are less critical.
It is therefore desirable to provide a digital circuit and dynamic power management scheme in which the power consumption level can be controlled dynamically without requiring a complex power supply, provides for use of a wider range of technologies and permits more efficient design with low transition overhead.